1. Field of the Invention
The invention relates to a method and apparatus for configuring devices attached to an interconnect in a computer system. Specifically, embodiments of the invention provide an improved device attachment method and apparatus for peripheral component interconnect (PCI) type interconnects.
2. Background
A computer, such as a desktop computer, workstation, server or similar machine, is started with a boot up sequence. During the boot up sequence the components of the computer system are initialized and prepared for operation. The length of the boot up sequence affects the user experience and productivity. A long boot up sequence frustrates a user and decreases the user's productivity.
Many components in a computer system are connected through an interconnect such as a shared bus or a point to point communication system. These interconnect systems allow the communication of data between the components of the computer system. For example, they allow the communication of data from a network card to a central processing unit or to the system memory. A computer system may have multiple interconnect systems connecting different sets of components. The different interconnect systems may have different architecture, protocols, speed and other differences in characteristics.
A commonly utilized interconnect system is a peripheral component interconnect (PCI). PCI type interconnects include several separately defined systems including conventional PCI (e.g. PCI 3.0), PCI-X and PCI-Express (PCI-e) defined by the PCI special interest group (PCI-SIG). Each of the PCI type interconnects discover attached devices by scanning the entire configuration space. The configuration space is an address space that is reserved for input/output (I/O) devices in the system. The entire configuration space is checked to determine, which devices, if any, are connected to the computer system. The configuration space is typically sparsely populated and scanning the entire configuration space is a slow process.
When a device is found in the configuration space, specialized configuration transaction packets or configuration cycles are utilized to identify and configure the device. These specialized packets and cycles add a level of complexity to the architecture of the interconnect and devices to support these configuration packets and cycles. The use of specialized configuration packets and cycles also makes it difficult to treat processor cores as devices, because the packets and cycles are generated by the (PCI controller in the I/O) chipset.
Some devices may have their device operational registers accessed by memory read and write operations. These devices are referred to as memory mapped and the address space is referred to as memory mapped I/O (MMIO). One or more registers in the configuration space contain the MMIO base address registers (BARs).
The PCI type interconnect system is designed for use with a single partition. A partition refers to a set of processor cores, memory and I/O resources of a computer system. A single operating system executes and manages resources for each partition of the computer system.